2016年12月5日 星期一

How to build FreeBSD for Raspberry Pi {1,2,3}

1.
On x86 or other fast platforms, use Crochet-Build to build images that can be written to sdcard and boot. Useful for initial installation, if you choose not to use pre-built -head or -stable snapshot images. It saves you some manual installation steps onto sdcard.

2.
Cross-build arm/arm64 binaries on a x86 PC, and then install kernel & world to upgrade existing disk partitions, e.g. put sdcard above in card reader and plug into PC.

make TARGET_ARCH=armv6 KERNCONF=RPI2 buildworld buildkernel 
make DESTDIR=/path/to/sdcard installkernel
mergemaster -A armv6 -D /path/to/sdcard -p
make DESTDIR=/path/to/sdcard installworld
mergemaster -A armv6 -D /path/to/sdcard -iU

3.
Cross-build arm/arm64 binaries, and then install them from running RPI mounting obj path
(Not working yet)

4.
Native build on RPI.
Very slow. RPi2/900MHz takes over 24 hours to complete. RPi1 takes a couple of days, close to a week. on x86 cross-build can be ~20x faster. You'd like to put obj files on NFS or other USB storage. sdcard I/O is slooooooow.

2016年10月16日 星期日

東大找到貓好發慢性腎衰竭的原因

貓型 AIM 缺乏人類或鼠AIM的腎修復機能,急性腎衰竭後無法修復腎近曲小管,因此演變為慢性腎衰竭的機率極高。找到原因之後,對於研究如何治療貓的急性腎衰竭,避免慢性化,以及利用在治療人類上,將有所幫助。

ネコに腎不全が多発する原因を究明 ~ネコではAIMが急性腎不全治癒に機能していない~

2015年5月4日 星期一

Google 模式

  • Google 模式/How Google Worls
  • ISBN:9789862419724

嚴格來說整書的重點只有一個: 人才。

找到最好的人才,讓他們自我演化。競爭跑得太快,傳統的工具已不適用。所以找到最能適應變化的人,讓他們自我驅動。

2015年3月24日 星期二

果菜市場看飛機

在濱江街跑道頭看飛機看久了,也是會好奇在果菜市場頂樓看飛機是什麼感覺。所以上個星期就上去一探究竟。

簡明版,上去看飛機的路徑是,從南面的魚市對面入口進去坐電梯,上到五樓之後往北面民族東路方向走到最外側,就會看到飛機了。

果菜市場建築物地上有六層樓,通常看飛機的地方實際上是五樓。六樓雖然也可以看到飛機,不過北面是內縮的設計,會比五樓後退許多。而且有天井、外牆等擋住視線,並不是很方便。

而上五樓要從南面,並不是每一個樓梯、電梯都可以。因為果菜市場的功能性和格局,並不是每一個電梯、樓梯都從樓頂通到地面。而且五樓事實上大部份面積是作為餐廳,其他樓梯電梯出到五樓其實是室內。而看飛機的地方事實上是餐廳後方的..陽台? 停車場? 也就是說,到了五樓之後是從側邊繞到餐廳的後面空地去。所以從南面入口進去是比較直接方便的。

拜樓高所賜,在果菜市場樓頂可以很清楚地看到飛機從西面降落10跑道的最後進場過程。別人拍的很多降落中的側面美照,也都是在這裡用長鏡頭捕捉。這裡看的是過程的完整性,和跑道頭被飛機洗臉的震撼感是不一樣的。

2014年10月1日 星期三

感同身受

在回來的高鐵上,翻出行前塞進平板的家政婦三田來看。原本只是為了打發時間,打算把之前看得斷斷續續的劇情,一次看個完整。

但是第一集看到一半,就流淚了。沒有辦法把一集看完。 因為,還有好多事沒有和你作,還有好多話,沒有跟你說。就如同劇情,你走得太突然。還沒有辦法接受這樣的事實,即使已擺在眼前。而已經七七了嗎? 就這樣和你永別了嗎?

虚構的劇情不管多麼荒謬,多少不合常理,能夠成功,始終是因為和讀者、觀眾的經驗契合,能夠打動人心產生共鳴。

2014年8月7日 星期四

Google Play 變成日文版本

所以這算是移民到不同國家版本的密技嗎?

作的是


  1. PC VPN 到日本網路,因為 Google Play 會認 IP 判斷國家。不可以用手機,因為似乎是手機 SIM 卡國別優先於 IP  國別
  2. 在 Google Play Books「買」了一本0元促銷的漫畫書。但因為先前有 Nexus 7 送的日幣額度,是用日幣結帳(0圓)。不確定沒有餘額也沒有日幣信用卡的話行不行。
  3. 接下來這個帳號下所有 Android  裝置通通重新要求確認了一遍 EULA, 就像被清除設定重來一遍一樣。

然後手機、平板上的 Google Play 看到的內容都變成日文版本。如排行榜等。商店也可以看到日本版有開放的 Play Video, Books, 但沒有日本還未開放的 Play Music。

2014年3月26日 星期三

What is possibly NVLink?

nVidia today announced NVLink claiming 5x-12x bandwidth of PCIe. And should be used together with IBM POWER systems.

What's possibly NVLink? what's it made of?

Previous tech on bus link increased bandwidth by growing bus width. 4-bit, 8-bit, 16-bit, 32-bit. e.g. like PCI bus or parallel bus. The problem of growing parallel bus width is that things got complicated when ilnk is wider and longer. It is harder and harder to keep all signals in sync. So the on-board PCI bus stopped at 64-bit. Parallel SCSI for inter-enclosure stopped at 16-bit. They both changed the direction toward high-speed serial links. So now we have PCIe and SAS.

But the high-speed serial link has its shortcomings too. Serial links though eliminated the need to sync across all signals, has high demand for serdes design, high-freq signal handling, etc. It is advancing, but not as easy as adding more signal links. The latest PCIe gen3 grew from 5GHz to 8GHz, less than doubled clock rate. The other bahdwidth improvement came from more efficient 128b/130b LDPC.

As the most bandwidth demanding component, GPU has lead the way of link and memory bandwidth. so we have various GDDR, ultra-side memory bus, and the primary user of PCIe has always been GPU before the AGP, graphics-centric bus, was done.

So what can NVLink be?

According to the slide nVidia provides, GPU and CPU still have PCIe link between them. So it is possible NVLink is used as a wider side channel for more efficient data movement. Much like what SLI and Crossfire did in the past. Only this time CPU joins the party. This makes it look more like the internal connect found in recent AMD APUs, but for inter-chip.

But where does the 5x-12x bandwidth come from?

It is possible that nVidia and IBM came out tech similar to QPI or HT for chip-level communications. Given that serial link clock is unlikely to get huge boost, It is more possible that NVLink gets the 5x ratio partly from higher clock/transaction. Say 1.5x for chip/board-optimized usage. The other mostly come wider link. PCIe is currently limited to x16 configuration. For specific usage optimization it is possible nVidia choose to widen the link, provided the link distance won't go too far. x32 link is a safe bet, and x64 is a bit ambitious.

Another inter-chip connect example is the newly disclosed OPIO from Intel, used on Haswell parts. 16-bit x 4 clusters/direction x 6.4GT/s gives 51.2GB/s per direction or "102.4GB/s bidirectional".OPIO is focused on on-package low-power interconnect. NVLink is unlikely to achieve the same level of power consumption.

The bad thing is nVidia is always light on technical details. Sometimes even distort or hide truths. The good is that IBM is more open in this regard. We will see.