- CPU/packet affinity to reduce context switches & memory copy
- Optimize DMA hardware to put data directly into CPU cache
- Optimize TCP/IP stacks for Intel SMP CPUs instead of TCP offloading
All are software-related optimizations, and they say you need a brand new Xeon server with onboard 82563/82564 or Pro/1000 PCI-Express NICs to have that.
Marketing really earns a lot. :D
Ref:
Intel® I/O Acceleration Technology Brief, Intel Document No.306484
Intel® I/O AT White Paper, Intel Document No.306517
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